1.1The Scope of Computer Architecture and Organization1
1.2Modeling Computer Organization3
1.2.1The Layered Structure of Computer Design Process3
1.2.2The RTL Model of Computer Organization4
1.2.3The Performance Model of a Computer System7
1.3A Historical Sketch of Computer Evolution10
1.4Representative Computer Families12
1.4.1The Pentium Family12
1.4.2The SPARC Family13
1.4.3The PowerPC Family14
1.5Perspectives of the Computer Evolution15
1.5.1The Challenges of a Billionª²Transistor IC15
1.5.2The New Role of the Nextª²Generation PC16
1.5.3Embedded Systems18
1.6Summary20
CHAPTER 2THE REPRESENTATION OF INFORMATION IN A COMPUTER
2.1Data Types Representing Information in a Computer21
2.2Representation of Fixedª²Point Unsigned Numbers22
2.2.1The General Positional Number System22
2.2.2The Representation of Fractional Numbers26
2.2.3Conversion Between Numbers of Different Representations27
Contents COMPUTER ORGANIZATION: PRINCIPLES£¬ANALYSIS,AND DESIGN 2.3Representation of Fixedª²Point Signed Numbers30
2.3.1Signª²Magnitude Representation30
2.3.2Two¡äs Complement Representation31
2.3.3Motivation for the Two¡äs Complement System34
2.3.4One¡äs Complement Representation36
2.4Binary Addition/Subtraction38
2.4.1Signª²Magnitude Addition/Subtraction38
2.4.2Two¡äs Complement Addition/Subtraction40
2.4.3One¡äs Complement Addition/Subtraction43
2.5Other Code Systems Using Bit Strings44
2.5.1Gray Codes44
2.5.2Decimal Codes45
2.5.3Character Codes47
2.6Summary48
Exercises48
CHAPTER 3LOGIC DESIGN OF COMBINATIONAL CIRCUITS
3.1Combinational Logic Functions and Expressions53
3.1.1Using Truth Table to Define a Combinational Logic Function53
3.1.2Primitive Combinational Functions and Basic Logic Operations54
3.1.3Boolean Algebra and Logic Expression56
3.1.4Canonical Logic Expressions57
3.2Karnaugh Maps for Simplification of Logic Functions60
3.3Implementation of Combinational Logic Functions63
3.3.1AND, OR, and NOT Gates63
3.3.2NAND and NOR Gates64
3.3.3XOR and XNOR Gates65
3.4Design of Combinational Logic Circuits67
3.4.1Design of a Full Adder67
3.4.2Rippleª²Carry Adder/Subtractor with External Logic for Subtraction 70
3.4.3Double Precision Addition/Subtraction72
3.4.4Rippleª²Carry Adder For Signª²Magnitude Representation73
3.5Dynamic Characteristics of Combinational Logic Circuits76
3.5.1Propagation Delay of Combinational Logic Circuits76
3.5.2Waveform Diagram of Combinational Logic Circuits76
3.5.3Hazards in Combinational Logic Circuits78
3.6Combinational MSI Modules82
3.6.1Multiplexer82
3.6.2Decoder/Demultiplexer86
3.6.3Encoder88
3.7Programmable Logic Devices90
3.7.1Programmable Logic Array (PLA)91
3.7.2Readª²Only Memory (ROM)92
3.7.3Programmable Array Logic (PAL)93
3.7.4Complex Programmable Logic Devices (CPLDs)95
3.7.5Fieldª²Programmable Gate Arrays (FPGAs)97
3.8Summary99
Exercises100
CHAPTER 4LOGIC DESIGN OF SEQUENTIAL CIRCUITS
4.1General Model of Sequential Circuits106
4.2Flipª²Flops107
4.2.1Analysis of A Simple SR Latch 108
4.2.2SR Flipª²Flop109
4.2.3JK Flipª²Flop111
4.2.4T Flipª²Flop113
4.2.5D Flipª²Flop114
4.2.6Practical Flipª²Flop Circuits115
4.3Analysis of Sequential Logic Circuits119
4.3.1From Circuit to Stateª²Transition Diagram119
4.3.2From Stateª²Transition Diagram to Finite State Machine121
4.4Synthesis of Sequential Logic Circuits122
4.5Sequential MSI Modules126
4.5.1Register126
4.5.2Shift Register127
4.5.3Counter128
4.6Design of a Finiteª²State Machine131
4.7Summary135
Exercises135
CHAPTER 5THE ARITHMETIC LOGIC UNIT
5.1The von Neumann Computer Model142
5.2Parallel Fast Adders143
5.2.1The Nature of Carry Propagation143
5.2.2The Rippleª²Carry Parallel Adder (Revisited)144
5.2.3The Fourª²bit Carry Lookª²ahead Adder145
5.2.4The Block Carry Lookª²ahead Circuit147
5.3Analysis of the Design of a Commercial ALU Chip150
5.3.1Organization of an ALU Based on an Adder150
5.3.2Design of the Input Circuit for Logic Operations152
5.3.3Analysis of the ALU for Arithmetic Operations154
5.4Methods for Designing Arithmeticª²Logic Units157
5.4.1Designing the ALU Using External Gates for Logic Operations157
5.4.2Designing an ALU Based on Standard ALU Chips159
5.4.3Redesigning the Input Circuit for the ALU 162
5.4.4Designing an ALU Using the Internal Circuit of an Adder165
5.4.5Redesigning the Output Circuit of the Adder167
5.4.6Comparison of Different Methods of Designing an ALU171
5.5Incorporating a Shifter in an ALU172
5.5.1Design of a Builtª²in Shifter in an ALU173
5.5.2Design of the Shifter as an Independent Unit178
5.5.3Design of a Barrel Shifter180
5.6Summary183
Exercises183
CHAPTER 6COMPLEX ARITHMETIC OPERATIONS
6.1Singleª²Precision Multiplication194
6.1.1The Basic Algorithm for Two¡äs Complement Multiplication194
6.1.2Fast Multiplication198
6.2Doubleª²Precision Multiplication206
6.2.1Special Requirement for the Algorithm206
6.2.2The Algorithm for Doubleª²Precision Multiplication of Positive Numbers207
6.2.3The Algorithm for Doubleª²Precision Multiplication of Two¡äs
Complement Numbers210
6.3Singleª²Precision Division213
6.4Doubleª²Precision Division218
6.4.1Special Requirements of the Algorithm218
6.4.2The Algorithm for Doubleª²Precision Division of Fractional Numbers219
6.4.3The Algorithm for Doubleª²Precision Division of Integer Numbers221
6.5Floatingª²Point Operations224
6.5.1The Representation of Floatingª²Point Numbers224
6.5.2The Algorithms for Floatingª²Point Operations228
6.5.3A Complete Algorithm for Floatingª²Point Addition/Subtraction229
6.5.4Implementation of Floatingª²Point Addition/Subtraction
by Sequential Logic231
6.6Summary232
Exercises232
CHAPTER 7INSTRUCTION SET ARCHITECTURE
7.1The Instruction Format239
7.2The Addressing Modes244
7.2.1Specifying the Operand in the Instruction Code245
7.2.2Specifying the Operand in a Register245
7.2.3Specifying the Operand in Memory245
7.2.4Specifying a Location Inside the Assemblyª²Language Program Code251
7.2.5A Case Study of Addressing Modes252
7.3Instruction Set Design 254
7.3.1Data Movement Instructions256
7.3.2Arithmeticª²Logic Instructions258
7.3.3Control Instructions259
7.4Reduced Instruction Set Computers (RISC)263
7.5Summary268
Exercises268
CHAPTER 8THE CENTRAL PROCESSING UNIT
8.1The Functions and Functional Parts of a CPU274
8.2The Basic Organization of the CPU275
8.2.1CPU Organization Based on Generalª²Purpose Registers276
8.2.2CPU Organization Based on an Accumulator277
8.2.3CPU Organization Based on a Processor Stack278
8.3The Structure of a CPU Based on an Accumulator279
8.3.1Design of an Accumulatorª²Based CPU Built on a Single Bus281
8.3.2Design of a Twoª²Bus or Threeª²Bus Accumulatorª²Based CPU286
8.3.3Design of an Accumulatorª²Based CPU Built on an ALU288
8.4The Structure of a CPU Based on Generalª²Purpose Registers291
8.4.1The Structure of a Generalª²Purpose Register Set291
8.4.2Design of a CPU Based on Generalª²Purpose Registers294
8.5CPU Bitª²Slice Device¡ªA Case Study295
8.6Summary299
Exercises299
CHAPTER 9THE CONTROL UNIT
9.1Functions and General Organization of a Control Unit304
9.2Preliminaries of Designing Control Circuits305
9.2.1Control Voltage Signals vs. Control Pulse Signals306
9.2.2Design of a Signal Generator Based on a Counter307
9.2.3Synchronous Control vs. Asynchronous Control308
9.2.4Asynchronous Circuits of Signal Generators309
9.3Design of the Sequential Control of Arithmetic Operations317
9.3.1Design of a Bitª²Serial Adder317
9.3.2Design of a Sequential Two¡äs Complement Multiplier322
9.4Design of Hardwired Control of a Simple Computer327
9.4.1Specification of a Simple RISC Processor327
9.4.2The Basic Instruction Cycle330
9.4.3Design of the Operation Chart for the Instruction Set332
9.4.4Design and Implementation of the Control Signals338
9.4.5Design and Implementation of the Datapath and Timing Signals342
9.5Design of the Microprogrammed Control of a Simple Computer346
9.5.1General Considerations for Microprogrammed Control346
9.5.2Design of the Datapath for Microprogrammed Control349
9.5.3Design of the Microinstruction Format for Microprogrammed Control354
9.5.4Design of the Flowchart for Microprogrammed Control357
9.5.5Obtaining the Microprogram List362
9.6Summary364
Exercises365
CHAPTER 10PRIMARY MEMORY
10.1The Memory Hierarchy374
10.1.1The Hierarchical Organization of a Memory System374
10.1.2Functionality and Performance of a Memory Hierarchy375
10.2The Organization of Main Memory377
10.2.1Functions and Characteristics of RAM Chips377
10.2.2Internal Organization of a RAM Chip378
10.2.3Basic Operations for Accessing RAM380
10.2.4Interconnection of RAM Chips for Larger Capacity382
10.3RAM Techniques for Enhanced Performance384
10.3.1Asynchronous DRAM385
10.3.2FPM and EDO386
10.3.3Synchronous DRAM (SDRAM)388
10.3.4Rambus DRAM (RDRAM)389
10.3.5Flash Memory vs. EEPROM390
10.3.6Split Bus392
10.4Cache Memory392
10.4.1Locality of Memory References393
10.4.2Mapping Functions394
10.4.3Write Policies401
10.4.4Replacement Algorithms402
10.4.5Cache Organization and Performance403
10.5Overall Primary Memory Organization405
10.5.1Serialª²Memory Narrowª²Bus Organization405
10.5.2Parallelª²Memory Wideª²Bus Organization406
10.5.3Parallelª²Memory Narrowª²Bus Organization407
10.5.4Interleavedª²Memory Narrowª²Bus Organization409
10.6Summary413
Exercises413
CHAPTER 11INPUT/OUTPUT
11.1Functions and Characteristics of I/O Subsystem417
11.2Secondary Storage420
11.2.1Magnetic Disk421
11.2.2Redundant Array of Independent Disks (RAID)424
11.2.3Optical Disks428
11.2.4Magnetic Tapes430
11.3Input/Output Accessing432
11.3.1Addressing I/O Registers432
11.3.2Programmed I/O434
11.3.3Interruptª²Driven I/O435
11.3.4Direct Memory Access438
11.4Exception and Exception Handling441
11.4.1Interrupt Request and Interrupt Acknowledge442
11.4.2Interrupt Identification442
11.4.3Interrupt Servicing and Interrupt Returning448
11.5The I/O Interfaces449
11.5.1I/O Bus Protocol449
11.5.2Parallel I/O Ports452
11.6Serial I/O Data Communication454
11.6.1Timing Synchronization of Serial Transmission454
11.6.2Error Detection and Correction Codes457
11.6.3Serial Interfaces and I/O Ports471
11.7Bus Standards476
11.7.1PCI (Peripheral Component Interconnect) Bus477
11.7.2SCSI (Small Computer System Interface) Parallel Interface480
11.7.3The USB Serial Bus485
11.7.4The FireWire Serial Bus493
11.7.5Switchedª²Fabric Architecture and InfiniBand495
11.8Summary497
Exercises498
CHAPTER 12PIPELINING
12.1The Basic Concept of Pipelining503
12.1.1Parallelism in Time vs. Parallelism in Space504
12.1.2Temporal Parallelism in Pipelining505
12.1.3Performance of the Pipeline510
12.2General Organization of a Pipeline511
12.2.1Synchronous Pipeline511
12.2.2Asynchronous Pipeline514
12.3Design of a Pipeline by Way of Functional Decomposition515
12.3.1Special Properties of Instruction Pipelines516
12.3.2The Mapping of the Dataflow Pattern to the Pipeline518
12.3.3Design of the Basic Datapath of the Pipeline 520
12.4The Design of the Pipeline from Hazard Analysis523
12.4.1Structural Hazards523
12.4.2Data Hazards¡ªA General Discussion524
12.4.3Data Hazard Analysis525
12.4.4Control Hazards534
12.4.5The Complete Datapath of the Pipeline540
12.5Superscalar Processor541
12.5.1Special Features of a Superscalar Processor541
12.5.2Conceptual Structure of a Superscalar Processor543
12.5.3Instructionª²Issue and Instructionª²Execute Policies544
12.6Summary547
Exercises548
REFERENCES554
1.1The Scope of Computer Architecture and Organization CHAPTER 1INTRODUCTION
