all Contents
3 ~lug in ASICS ................................ 45
3. 1 Introduction.. ... .. ... .... .. ... ..... ...... ... .... ...... ... ....... .... .... ...... .. .... .. ..... .. .... ...... .... ... ... 45
3.2 Prelayout amings
yout nining. ... ...... ........ ... ... ........ .. ........ .. .... ... .... ... ... ... .... ... ... ... .. ... .... ....... 48
3'2. 1 RTL VB. Gate-duel Tabing. ... ..... ............. ... .......... .... ......... ... ... .. .... .... .. .... 49
3'2'2 ~ng in RTL Code.. ... .... .... ... ... ... ........................ ... ...... ... ... .. .. ... ... ... ... .... 50
3.2 .3 Delsy with a Continuotts Assignment
Cont6nts ix
4.4 TIming
List of FigUres
Fig. 1. 1 chical ASIC Design Flow. .... .... ... ... .... ......... ..... ... .. ... .... ... ...... .... ............... .2
Fig. 1.2 Spiral Design Flow..................... ......................................................... ....... .4
Fig. 1.3 STA Measures Path Delays Through a Circuit ... .. .... ... ......... ......... ... .... ..... 7
Fig. 1.4 STA Is Best Suited for Use on Synchronous Circuits.....'........... ...... .... ... ..8
Fig. 1.5 Time Available for Propagation Between Two Flip-Flops
Depends on Clock Skew and Flip-Flop Setup Time ....... ... ...... ......... .... .. ..9
Fig. 1.6 Block-Diagram of the System in Example 1. 1. .... ... .... ....... .... ... .. ... ... ....... 14
Fig. 1.7 Merged Read Diagram of the CPU Plus the ED~ .. ... ...... ... ........ ... .... 15
Fig. 2. 1 Single Clock Pulse: (a) POsitive Clock Pulse (b) Negative
-
Clock
...
xll LiSt Of Fiaures
cureS
Fig. 2. 18 acme Available for Propagation Between Two Flip-Flops
Depends on Clock Skew and Flip-Flop Setup nine....................... ... .... 33
fig. 2. 19 CAD TOols Offer Two Delay Models .................... ... .. ......... .......... ... ... ..... 35
ig. 2.20 Phase-Locked Loop Block Diagram..... ... ..... ... ....... ... .. ...... ... ....... ... ........ 38
ac. 2.21 Ideal PLL Behavior... .... ... ..... ... .. .... ....... ...... ...... ... ...... ... ... ... ... .. .... ... .... .... 40
fig. 2.22 Nonideal PLL Behavior ........... .. ..... ................... ....... .. ... ....... ........... ... .... 42
ac. 3. 1 Accurate Models Require inclusion Of Parasitic Capacitors........ ........... 46
ig. 3.2 Components of Circuit Delsy: Input Slew Rate, Inherent G8te
Delay, Line Propagation Delay, Fanout Load... ........................... .......... 47
ac. 3.3 Parasitic Cap8Citance Of a Metal Line................ .................... ... ....... ....... 48
ig. 3.4 Circuits Can Be Represented as RTL Code or insbotiated
Gates. .... ... ... ... .... ... ... .. .. .. ........ ... ..... .... ... .... ... .. ..... ....... .. .. .. ... .. .... .... .. .... ..... 49
ig. 3.5 Delays of Entire Modules Are Easy to Implement in an HDL ............... 51
Fig. 3.6 ~ Tabing Diagr~. ... .... ... ... ... ... ...... ..... ... ... ... .... .. ...... .. .... ... ... ... ... ... ..... 52
fig. 3. 7 Signals Comsponchg to Ex~ple 3.3. ....... ...... ........... ... ...... .... ... ... .. ...... 54
ig' 3'8 Signals from the Blocking Assignment Statements with Reghar
Delays from Ex~ple 3.4.. .... .. ... .... .... .. .. ............ ... ...... .... ...... ....... ..... .. .... 55
fig. 3.9 Signals from BIOCchg Assignment Statements
Intra-Assignment Delays from Ex~ple 3.5......................................... 57
ig. 3.10 Signals horn Nonblocbog Assignment Statements with
Intra-Assignment Delays from Ex~ple 3.6 .......... ............... ................ 59
ac. 3. 11 Partial ~g Diagram for a SynchronOus ~...... .... .. .. ........ .... .. ... .. 60
ig. 3. 12 The set-input--delay Command Adds Additional Delay to
Module input ffoes.................... .'. ......................................................... 68
ig. 3.13 The set--output-delay Command Adds Additional Delsy tO
Module Output foes.............. ....... .. ..... ... .. ....... .... ...... .. ........ ...... .... ....... 68
ig. 3.14 Circuit Corresponding to the SDF Constraint roe of
Example 3' 14 .. ... ... ... ...... ................. ......... .. .. ... .... ... .. ... ..... .. .. .. .... ... ...... ..... 75
ac. 3. 15 Circuit COrresponding to the SDF ale of Ex~ple 3. 15 ...................... 77
ig. 3'16 Parasitic Capablers Edest Between All Layers Of a Process ................ 85
ac. 3. 17 ConduCtors Hare Both Plate and Fringe CSPachrs.. .... .... .. .. ......... ... .. 86
ig' 3'18 Fringe Capadtsnce Can Be Modeled as a Cylindrical
Conductor.... ....................... ....................... ..... .............................. ........... 87
De. 3. 19 Line Resistance is Meas~d in Squ~B. .... ... .... ..... ..... ... ... ...... ... ... .... .. 90
ig. 3.20 Distributed RC Model Provides Greater Accuracy than
Lamped Model... ... ... .... .. ... .. ... ..... ... .. .... .. ... ... ... ... .... ......... ....... ... ... ..... .. .. ... 92
ig. 4. 1 CPLD StrU~................. ........................ ............................................. 102
ig. 4.2 Simpered FPGA
...
LiSt Of Figures xlii
ig. 4.7 Actel ACT 3 Thchg Model (Values Shown for Actel A1425A-3
at Worst Case Commercial
List of Whies
Table 1. 1 Delay Paths of FigUre 1 '3.............. ... .... ... .. ....... ... .... ............. ... ... ... ...... .... .8
Table 1'2 Paths Measured in STA'..... ... ............... .. .... ...... ............................. ......... 10
Table 1'3 Truth Table for Circuit in Fibre 1.3 .. ... ...... .... ... ... ...... .... .... ... ... .. ... ... .. .. 10
Table 3' 1 Synchronous Memory Timing Parameters................... ......................... 60
Table 3.2 chical Metal Widths for 0.sum Process ...... ... ... ... .... ....... .. ... ... .... .. ... .... 88
Table 3.3 beteal Capacitance Values for 0.8~
