目录
第1部分 计算机系统I——单周期CPU设计 ...................................................................................... 1
第1章 SysI-Lab1实验准备 ...................................................................................... 3
1.1实验工具 ...................................................................................... 3
1.2背景知识
......................................................................................... 4
1.2.1
FPGA的发展历程................................................................. 4
1.2.2
Verilog基础知识 ................................................................... 6
1.3实验环境配置
.................................................................................12
1.3.1
Linux环境配置 ....................................................................12
1.3.2
SPICE仿真反相器 ...............................................................13
1.3.3
Logisim电路仿真 .................................................................15
1.4
Verilator仿真测试 ..........................................................................16
1.5
Vivado操作流程.............................................................................18
1.5.1 FPGA上的 Verilog实践.......................................................28
1.
5.2以二选一多路选择器为例 ......................................................35 思考及练习 ............................................................................................36
第 2章 SysI-Lab2多路选择器 ..................................................................38
2.1实验工具
........................................................................................38
2.
2多路选择器设计 ..............................................................................38
2.2.1基本概念
..............................................................................38
2.
2.2电路级别的实现....................................................................39
2.
2.3四路选择器的实现 ................................................................39
2.3实验步骤
........................................................................................41 思考及练习 ............................................................................................41
第 3章 SysI-Lab3七段数码管 ..................................................................42
3.1实验工具
........................................................................................42
3.2背景知识
........................................................................................42
3.
2.1复合多路选择器....................................................................42
3.2.2译码器
.................................................................................43
计算机系统贯通课程实践教材（RISC-V架构）
3.2.3时钟分频器 ..........................................................................43
3.2.4 NEXYS A7-100T七段管 ......................................................43
3.3实验步骤 ........................................................................................45 思考及练习 ............................................................................................46
第 4章 SysI-Lab4全加减法器 ..................................................................47
4.1实验工具 ........................................................................................47
4.2加法器设计.....................................................................................47
4.2.1加法器实验原理....................................................................47
4.2.2加法器实验步骤....................................................................50
4.3加减法器设计 .................................................................................51
4.3.1加减法器实验原理 ................................................................51
4.3.2 64b加减法器实验步骤 ..........................................................52 思考及练习 ............................................................................................52
第 5章 SysI-Lab5时序电路设计 ...............................................................53
5.1实验工具 ........................................................................................53
5.2时序电路设计基础...........................................................................53
5.2.1有限状态机 ..........................................................................53
5.2.2计数器 .................................................................................55
5.2.3分频器 .................................................................................55
5.3计时器设计.....................................................................................56
5.3.1 4位二进制计数器 .................................................................56
5.3.2 2位 BCD码计数器 ..............................................................57
5.3.3计时器实验步骤....................................................................57
5.4乘法器设计.....................................................................................58
5.4.1乘法器实验原理....................................................................58
5.4.2 Booth算法 ..........................................................................60
5.4.3乘法器实验步骤....................................................................61 思考及练习 ............................................................................................62
第 6章 SysI-Lab6卷积核实现 ..................................................................63
6.1实验工具 ........................................................................................63
6.2背景知识 .......................................................................................63
6.2.1移位寄存器 ..........................................................................63
6.2.2 SystemVerilog语法...............................................................64
6.2.3 Ready-Valid握手 .................................................................66
6.3实验原理 ........................................................................................67
7.5.1理解跳转表 ..........................................................................86
7.5.2回顾冒泡排序算法 ................................................................87
7.5.3理解简单 RISC-V程序 .........................................................87
7.5.4理解递归汇编程序 ................................................................88
7.5.5理解 switch语句产生的跳转表 ..............................................89
7.6实验步骤 ........................................................................................90
7.6.1冒泡排序的汇编实现 .............................................................90
7.6.2斐波那契数列的汇编实现 ......................................................90
7.6.3通过调试破解密钥 ................................................................91
7.6.4 RISC-V Binary Bomb...........................................................92 思考及练习 ............................................................................................93
第 8章 SysI-Lab8单周期 CPU设计........................................................94
8.1实验工具 ........................................................................................94
8.2背景知识 ........................................................................................94
8.2.1 RISC-V指令格式 .................................................................94
8.2.2数据通路..............................................................................95
8.2.3控制单元..............................................................................97
8.3 RISC-V基础指令 ......................................................................... 101
8.4实验原理 ...................................................................................... 114
8.4.1 Memory设计 ..................................................................... 114
8.4.2数据通路设计 ..................................................................... 116
数据冒险............................................................................
9.3.2实现暂停机制 ..................................................................... 128
9.4 DRAM和 BRAM的区别.............................................................. 128
9.5 BRAM的使用.............................................................................. 129
9.6实验目标 ...................................................................................... 130
9.7实验步骤 ...................................................................................... 131 思考及练习 .......................................................................................... 132
第 10章 SysII-Lab2流水线冒险的解决.................................................... 133
10.1实验工具 .................................................................................... 133
10.2实验原理 .................................................................................... 133
10.2.1流水线的旁路机制 ........................................................... 133
10.2.2 Axi-lite总线协议 ............................................................ 134
10.3实验步骤 .................................................................................... 136 思考及练习 .......................................................................................... 136
第 11章 SysII-Lab3卷积加速器.............................................................. 137
11.1实验工具 .................................................................................... 137
11.2实验原理 .................................................................................... 137
11.2.1外设编程接口.................................................................. 137
11.2.2 MMIO机制及定义 .......................................................... 138
11.2.3卷积加速器的 I/O映射及操作 ......................................... 139
实验工具 ....................................................................................
13.2背景知识 .................................................................................... 150
13.2.1 RISC-V中的中断和异常.................................................. 150
13.2.2上下文处理 ..................................................................... 152
13.2.3异常处理程序和时钟中断 ................................................. 152
13.3实验步骤 .................................................................................... 152
13.3.1准备工程 ........................................................................ 152
13.3.2开启异常处理.................................................................. 154
13.3.3实现上下文切换 .............................................................. 155
13.3.4实现异常处理函数 ........................................................... 156
13.3.5实现时钟中断相关函数 .................................................... 156
13.3.6实验样例 ........................................................................ 157 思考及练习 .......................................................................................... 157
第 14章 SysII-Lab6异常流水线.............................................................. 158
14.1实验工具 .................................................................................... 158
14.2实验原理 .................................................................................... 158
14.2.1 RISC-V特权级 ............................................................... 158
14.2.2控制和状态寄存器 ........................................................... 158
14.2.3异常和中断 ..................................................................... 159
14.3异常流水线设计 .......................................................................... 162
14.3.1实现 CSR指令................................................................ 162
15.3.4实验样例 ........................................................................ 174 思考及练习 .......................................................................................... 176
第 16章 SysII-Lab8软硬件协同的尝试.................................................... 177
16.1实验工具 .................................................................................... 177
16.2实验原理 .................................................................................... 177
16.2.1整体架构设计.................................................................. 177
16.2.2硬件外围设计.................................................................. 178
16.3编译内核 .................................................................................... 178
16.4外围准备 .................................................................................... 179
16.4.1 Bootloader代码 .............................................................. 179
16.4.2生成下板代码.................................................................. 180
16.4.3建立工程文件.................................................................. 180
16.4.4观察下板现象.................................................................. 181
16.4.5 Vivado仿真运行 ............................................................. 182
16.5实验步骤 .................................................................................... 182 思考及练习 .......................................................................................... 182
第 3部分计算机系统 III——定制化内核 + CPU综合设计 .............183
第 17章 SysIII-Lab1动态分支预测 ......................................................... 185
17.1实验工具 .................................................................................... 185
18.2.4 Cache与 Memory的数据传输.......................................... 196
18.3 Cache控制逻辑 .......................................................................... 198
18.3.1初始化 IDLE状态........................................................... 199
18.3.2读事务执行 READ状态 .................................................. 199
18.3.3写事务执行 WRITE状态 ................................................ 200
18.4 Cache的完整结构 ....................................................................... 201
18.5实验步骤 .................................................................................... 203
18.5.1实验目标 ........................................................................ 203
18.5.2仿真测试 ........................................................................ 204
18.5.3上板验证 ........................................................................ 205 思考及练习 .......................................................................................... 205
第 19章 SysIII-Lab3 RV64虚拟内存管理 ............................................... 206
19.1实验工具 .................................................................................... 206
19.2虚拟内存布局.............................................................................. 206
19.3 SATP寄存器.............................................................................. 207
19.4虚实地址转换.............................................................................. 208
19.4.1虚拟地址和物理地址........................................................ 208
19.4.2 RISC-V Sv39模式页表项 ................................................ 208
19.4.3 RISC-V地址转换............................................................ 209
19.5实验步骤 .................................................................................... 209
20.4.3中断处理 ........................................................................ 221
20.4.4添加系统调用.................................................................. 223
20.4.5修改内核启动.................................................................. 223
20.4.6编译及测试 ..................................................................... 223 思考及练习 .......................................................................................... 224
第 21章 SysIII-Lab5 RV64缺页异常处理 ............................................... 225
21.1实验工具 .................................................................................... 225
21.2背景知识 .................................................................................... 225
21.2.1虚拟内存管理.................................................................. 225
21.2.2缺页异常 ........................................................................ 226
21.3实验步骤 .................................................................................... 227
21.3.1准备工程 ........................................................................ 227
21.3.2实现虚拟内存管理 ........................................................... 228
21.3.3任务初始化 ..................................................................... 230
21.3.4实现缺页异常处理 ........................................................... 230
21.3.5编译及测试 ..................................................................... 231 思考及练习 .......................................................................................... 232
第 22章 SysIII-Lab6 fork机制............................................................... 233
22.1实验工具 .................................................................................... 233
22.2 fork基础知识 ............................................................................. 233
23.2.1 RISC-V Sv39分页模式.................................................... 241
23.2.2 Axi-lite总线模型 ............................................................ 243
23.2.3 MMU模块 ..................................................................... 243
23.3实验步骤 .................................................................................... 244
23.3.1实验目标 ........................................................................ 244
23.3.2仿真测试 ........................................................................ 244
23.3.3上板验证 ........................................................................ 244 思考及练习 .......................................................................................... 244
第 24章 SysIII-Lab8完成自己的计算机系统 ............................................ 245
24.1实验工具 .................................................................................... 245
24.2实验目标 .................................................................................... 245
24.3实验原理 .................................................................................... 246
24.3.1用户态实现及中断完善 .................................................... 246
24.3.2地址转换后备缓冲器........................................................ 246
24.3.3 MMIO与外设................................................................. 247
24.4设计范例 .................................................................................... 247
24.4.1范例一：指令集扩展........................................................ 247
24.4.2范例二：运行较为完善的 Kernel ...................................... 252 思考及练习 .......................................................................................... 259
第4部分 附录及常见问题.................................. 261
附录A 硬件描述语言常见语句及电路图 ..................................263
附录B 配置IP核..................................275
附录C 常见问题..................................287
参考文献..................................294
