This book describes the architecture and characteristics of devices in reference to the development stages of FPGA; uses Verilog language as the hardware description language to describe the design of digital system, so as to ensure the correctness of design functions to pass the simulation verification; in Vivado design suite, the Timing Convergence is achieved through RTL analysis, integration, and implementation of layout and wiring, which meets the design requirements for performance. This book also introduces tips and key points about synchronous design, advanced integration and other features. The design process and methods of DSP system and embedded system are also introduced; and the book finally elucidates the above-mentioned design methods with several design examples.

Meng Xianyuan, professor of Department of Electronic Engineering, Tsinghua University, has been engaged in research and teaching of EDA-related technology for years. He has accumulated over 20 years’ experiences in FPGA technological research and project development.